This project is in a trial period, be cautious while contributing. Setup can still change before being approved as a libre project.
Component Approved Translated Unfinished Unfinished words Unfinished characters Untranslated Checks Suggestions Comments
SpinalHDL/Libraries/EDA/altera/qsysify CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Libraries/EDA/altera/quartus_flow CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Libraries/EDA/index CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Libraries/fiber CC0-1.0 0 0 0 0 0 9 0
SpinalHDL/Libraries/flow CC0-1.0 0 0 0 0 2 2 0
SpinalHDL/Libraries/fragment CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Libraries/fsm CC0-1.0 0 0 0 0 5 3 0
SpinalHDL/Libraries/Graphics/colors CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Libraries/Graphics/index CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Libraries/Graphics/vga CC0-1.0 0 0 0 0 0 1 0
SpinalHDL/Libraries/index CC0-1.0 0 0 0 0 1 0 0
SpinalHDL/Libraries/IO/index CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Libraries/IO/readableOpenDrain CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Libraries/IO/tristate CC0-1.0 0 0 0 0 0 1 0
SpinalHDL/Libraries/Misc/index CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Libraries/Misc/PLIC/plic_mapper CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Libraries/Misc/service_plugin CC0-1.0 0 0 0 0 6 0 0
SpinalHDL/Libraries/Pipeline/index CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Libraries/Pipeline/introduction CC0-1.0 0 0 0 0 1 0 0
SpinalHDL/Libraries/regIf CC0-1.0 0 0 0 0 1 12 0
SpinalHDL/Libraries/stream CC0-1.0 0 0 0 0 1 2 0
SpinalHDL/Libraries/utils CC0-1.0 0 0 0 0 8 5 0
SpinalHDL/Libraries/vexriscv CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/miscelenea/chisel CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/miscelenea/core/core_components CC0-1.0 0 0 0 0 0 2 0
SpinalHDL/miscelenea/core/elements CC0-1.0 0 0 0 0 5 0 0
SpinalHDL/miscelenea/frequent_errors CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/miscelenea/index CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Other language features/analog_inout CC0-1.0 0 0 0 0 1 0 0
SpinalHDL/Other language features/assertion CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Other language features/index CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Other language features/report CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Other language features/scope_property CC0-1.0 0 0 0 0 0 1 0
SpinalHDL/Other language features/stub CC0-1.0 0 0 0 0 0 6 0
SpinalHDL/Other language features/utils CC0-1.0 0 0 0 0 3 4 0
SpinalHDL/Other language features/vhdl_generation CC0-1.0 0 0 0 0 1 0 0
SpinalHDL/Semantic/assignments CC0-1.0 0 0 0 0 3 6 0
SpinalHDL/Semantic/index CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Semantic/rules CC0-1.0 0 0 0 0 0 1 0
SpinalHDL/Semantic/when_switch CC0-1.0 0 0 0 0 4 2 0
SpinalHDL/Sequential logic/index CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Sequential logic/memory CC0-1.0 0 0 0 0 21 3 0
SpinalHDL/Sequential logic/registers CC0-1.0 0 0 0 0 4 1 0
SpinalHDL/Simulation/bootstraps CC0-1.0 0 0 0 0 10 0 0
SpinalHDL/Simulation/clock CC0-1.0 0 0 0 0 26 2 0
SpinalHDL/Simulation/engine CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Simulation/examples/asynchronous CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Simulation/examples/dual_clock_fifo CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Simulation/examples/index CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Simulation/examples/single_clock_fifo CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Simulation/examples/synchronous CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Simulation/examples/uart_decoder CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Simulation/examples/uart_encoder CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Simulation/index CC0-1.0 0 0 0 0 1 2 0
SpinalHDL/Simulation/install/GHDL CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Simulation/install/Icarus Verilog CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Simulation/install/index CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Simulation/install/VCS CC0-1.0 0 0 0 0 6 1 0
SpinalHDL/Simulation/install/Verilator CC0-1.0 0 0 0 0 1 1 0
SpinalHDL/Simulation/sensitive CC0-1.0 0 0 0 0 2 0 0
SpinalHDL/Simulation/signal CC0-1.0 0 0 0 0 10 0 0
SpinalHDL/Simulation/simulator_specifics CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Simulation/threadFull CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Simulation/threadLess CC0-1.0 0 0 0 0 2 0 0
SpinalHDL/Structuring/area CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Structuring/blackbox CC0-1.0 0 0 0 0 4 1 0
SpinalHDL/Structuring/clock_domain CC0-1.0 0 0 0 0 24 3 0
SpinalHDL/Structuring/components_hierarchy CC0-1.0 0 0 0 0 3 7 0
SpinalHDL/Structuring/function CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Structuring/index CC0-1.0 0 0 0 0 0 0 0
SpinalHDL/Structuring/naming CC0-1.0 0 0 0 0 2 2 0
SpinalHDL/Structuring/parametrization CC0-1.0 0 0 0 0 1 4 0
Glossary SpinalDoc-RTD CC0-1.0 25% 0 0 0 0 0 0 0

Overview

Project website spinalhdl.github.io/SpinalDoc-RTD
Instructions for translators

SpinalHDL的使用说明
Project maintainers User avatar Readon User avatar SpinalHDL-CN User avatar tsy0123
Translation license CC0-1.0 SpinalHDL/Libraries/EDA/altera/qsysify SpinalHDL/Libraries/EDA/altera/quartus_flow SpinalHDL/Libraries/EDA/index SpinalHDL/Libraries/fiber SpinalHDL/Libraries/flow SpinalHDL/Libraries/fragment SpinalHDL/Libraries/fsm SpinalHDL/Libraries/Graphics/colors SpinalHDL/Libraries/Graphics/index SpinalHDL/Libraries/Graphics/vga SpinalHDL/Libraries/index SpinalHDL/Libraries/IO/index SpinalHDL/Libraries/IO/readableOpenDrain SpinalHDL/Libraries/IO/tristate SpinalHDL/Libraries/Misc/index SpinalHDL/Libraries/Misc/PLIC/plic_mapper SpinalHDL/Libraries/Misc/service_plugin SpinalHDL/Libraries/Pipeline/index SpinalHDL/Libraries/Pipeline/introduction SpinalHDL/Libraries/regIf SpinalHDL/Libraries/stream SpinalHDL/Libraries/utils SpinalHDL/Libraries/vexriscv SpinalHDL/miscelenea/chisel SpinalHDL/miscelenea/core/core_components SpinalHDL/miscelenea/core/elements SpinalHDL/miscelenea/frequent_errors SpinalHDL/miscelenea/index SpinalHDL/Other language features/analog_inout SpinalHDL/Other language features/assertion SpinalHDL/Other language features/index SpinalHDL/Other language features/report SpinalHDL/Other language features/scope_property SpinalHDL/Other language features/stub SpinalHDL/Other language features/utils SpinalHDL/Other language features/vhdl_generation SpinalHDL/Semantic/assignments SpinalHDL/Semantic/index SpinalHDL/Semantic/rules SpinalHDL/Semantic/when_switch SpinalHDL/Sequential logic/index SpinalHDL/Sequential logic/memory SpinalHDL/Sequential logic/registers SpinalHDL/Simulation/bootstraps SpinalHDL/Simulation/clock SpinalHDL/Simulation/engine SpinalHDL/Simulation/examples/asynchronous SpinalHDL/Simulation/examples/dual_clock_fifo SpinalHDL/Simulation/examples/index SpinalHDL/Simulation/examples/single_clock_fifo SpinalHDL/Simulation/examples/synchronous SpinalHDL/Simulation/examples/uart_decoder SpinalHDL/Simulation/examples/uart_encoder SpinalHDL/Simulation/index SpinalHDL/Simulation/install/GHDL SpinalHDL/Simulation/install/Icarus Verilog SpinalHDL/Simulation/install/index SpinalHDL/Simulation/install/VCS SpinalHDL/Simulation/install/Verilator SpinalHDL/Simulation/sensitive SpinalHDL/Simulation/signal SpinalHDL/Simulation/simulator_specifics SpinalHDL/Simulation/threadFull SpinalHDL/Simulation/threadLess SpinalHDL/Structuring/area SpinalHDL/Structuring/blackbox SpinalHDL/Structuring/clock_domain SpinalHDL/Structuring/components_hierarchy SpinalHDL/Structuring/function SpinalHDL/Structuring/index SpinalHDL/Structuring/naming SpinalHDL/Structuring/parametrization SpinalDoc-RTD
an hour ago

String statistics

Strings percent Hosted strings Words percent Hosted words Characters percent Hosted characters
Total 11,308 99,354 640,046
Source 5,654 49,677 320,023
Approved 49% 5,616 49% 49,627 49% 319,668
Waiting for review 1% 60 1% 79 1% 576
Translated 100% 11,308 100% 99,354 100% 640,046
Needs editing 0% 0 0% 0 0% 0
Read-only 49% 5,632 49% 49,648 49% 319,802
Failing checks 2% 258 1% 1,520 1% 11,577
Strings with suggestions 2% 278 4% 4,633 4% 29,595
Untranslated strings 0% 0 0% 0 0% 0
Last 12 months Previous

Activity in last 12 months

0 changes 0 changes 0 changes 0 changes 0 changes 0 changes 0 changes 0 changes 0 changes 0 changes 0 changes 0 changes 0 changes 0 changes 0 changes 18,418 changes 0 changes 2,436 changes 0 changes 72 changes 0 changes 193 changes 0 changes 81 changes
May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr

Quick numbers

99,354
Hosted words
11,308
Hosted strings
100%
Translated
2
Contributors
and previous 30 days

Trends of last 30 days

+1%
Hosted words
+100%
+1%
Hosted strings
+100%
—
Translated
+100%
—
Contributors
+100%
Language Approved Translated Unfinished Unfinished words Unfinished characters Untranslated Checks Suggestions Comments
English 99% 0 0 0 0 46 0 0
Chinese (Simplified) 99% 0 0 0 0 212 278 0
User avatar None

Repository notification received

  1. SpinalDoc-RTD
  2. index
GitHub: https://github.com/SpinalHDL-CN/SpinalDoc-RTD, master 2 weeks ago
User avatar None

Repository notification received

  1. SpinalDoc-RTD
  2. index
GitHub: https://github.com/SpinalHDL-CN/SpinalDoc-RTD, master 2 weeks ago
User avatar Readon

Changes pushed

  1. SpinalDoc-RTD
  2. index
Changes pushed 2 weeks ago
User avatar None

Changes pushed

  1. SpinalDoc-RTD
  2. index
Changes pushed 2 weeks ago
User avatar Readon

Changes committed

  1. SpinalDoc-RTD
  2. SpinalHDL/Libraries/utils
  3. Chinese (Simplified)
Changes committed 2 weeks ago
User avatar Readon

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Libraries/utils
  3. Chinese (Simplified)
from the first one to the last one
从第一个节点到最后一个节点
2 weeks ago
User avatar Readon

Translation changed

  1. SpinalDoc-RTD
  2. SpinalHDL/Libraries/utils
  3. Chinese (Simplified)
from the first one to the last one
从第一个节点到最后一个节点
2 weeks ago
User avatar Readon

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Libraries/utils
  3. Chinese (Simplified)
There is also an ``ResetCtrl.asyncAssertSyncDeassertDrive`` version of tool which directly assign the ``clockDomain`` reset with the filtered value.
另外还有一个 ``ResetCtrl.asyncAssertSyncDeassertDrive`` 版本的工具，它直接使用筛选后的值新构造的复位信号作为 ``clockDomain`` 这个时钟域的复位赋值。
2 weeks ago
User avatar Readon

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Libraries/utils
  3. Chinese (Simplified)
ClockDomain which will use the filtered value
返回将使用所筛选值的新复位信号对齐的时钟域(ClockDomain)
2 weeks ago
User avatar Readon

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Libraries/utils
  3. Chinese (Simplified)
Signal that should be filtered
被筛选的信号输入的异步信号，用于触发复位
2 weeks ago
Browse all project changes