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Overview

Project website spinalhdl.github.io/SpinalDoc-RTD
Instructions for translators

SpinalHDL的使用说明
Project maintainers User avatar Readon User avatar SpinalHDL-CN User avatar tsy0123
Translation license Creative Commons Zero v1.0 Universal
Translation process
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  • Translation suggestions can be made.
  • Translations are reviewed by dedicated reviewers.
  • Any authenticated user can contribute.
  • The translation uses bilingual files.
Source code repository git@github.com:SpinalHDL-CN/SpinalDoc-RTD.git
Repository branch master
Last remote commit don't fail on check link 29e24f116
Dolu1990 authored 2 weeks ago
Last commit in Weblate Translated using Weblate (Chinese (Simplified)) 9f25c5b8c
User avatar tsy0123 authored 3 months ago
Weblate repository https://hosted.weblate.org/git/spinaldoc-rtd/index/
File mask source/locale/*/LC_MESSAGES/SpinalHDL/Libraries/EDA/altera/qsysify.po
4 weeks ago

String statistics

Strings percent Hosted strings Words percent Hosted words Characters percent Hosted characters
Total 34 284 2,276
Source 17 142 1,138
Approved 50% 17 50% 142 50% 1,138
Waiting for review 0% 0 0% 0 0% 0
Translated 100% 34 100% 284 100% 2,276
Needs editing 0% 0 0% 0 0% 0
Read-only 50% 17 50% 142 50% 1,138
Failing checks 0% 0 0% 0 0% 0
Strings with suggestions 0% 0 0% 0 0% 0
Untranslated strings 0% 0 0% 0 0% 0
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User avatar None

Changes committed

  1. SpinalDoc-RTD
  2. SpinalHDL/Libraries/EDA/altera/qsysify
  3. Chinese (Simplified)
Changes committed 3 months ago
User avatar tsy0123

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Libraries/EDA/altera/qsysify
  3. Chinese (Simplified)
Basically, the QSysify tool can be setup with a list of interface ``emitter`` `(as you can see here) <https://github.com/SpinalHDL/SpinalHDL/blob/764193013f84cfe4f82d7d1f1739c4561ef65860/lib/src/main/scala/spinal/lib/eda/altera/QSys.scala#L12>`_
基本上，QSysify工具可以使用接口 ``emitter`` 列表进行设置 `（如您在此处看到的） <https://github.com/SpinalHDL/SpinalHDL/blob/764193013f84cfe4f82d7d1f1739c4561ef65860/lib/src/main/scala/spinal/lib/eda/altera/QSys.scala#L12>`_
3 months ago
User avatar None

Changes committed

  1. SpinalDoc-RTD
  2. SpinalHDL/Libraries/EDA/altera/qsysify
  3. Chinese (Simplified)
Changes committed 3 months ago
User avatar tsy0123

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Libraries/EDA/altera/qsysify
  3. Chinese (Simplified)
You can create your own emitter by creating a new class extending `QSysifyInterfaceEmiter <https://github.com/SpinalHDL/SpinalHDL/blob/764193013f84cfe4f82d7d1f1739c4561ef65860/lib/src/main/scala/spinal/lib/eda/altera/QSys.scala#L24>`_
您可以通过创建一个扩展 `QSysifyInterfaceEmiter的新类来创建自己的发射器 <https://github.com/SpinalHDL/SpinalHDL/blob/764193013f84cfe4f82d7d1f1739c4561ef65860/lib/src/main/scala/spinal/lib/eda/altera/QSys.scala #L24>`_ 的新类来创建自己的发射器(emitter)
3 months ago
User avatar tsy0123

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Libraries/EDA/altera/qsysify
  3. Chinese (Simplified)
Basically, the QSysify tool can be setup with a list of interface ``emitter`` `(as you can see here) <https://github.com/SpinalHDL/SpinalHDL/blob/764193013f84cfe4f82d7d1f1739c4561ef65860/lib/src/main/scala/spinal/lib/eda/altera/QSys.scala#L12>`_
基本上，QSysify 工具可以使用接口“发射器” ``emitter`` 列表进行设置 `（如您在此处看到的）<https://github.com/SpinalHDL/SpinalHDL/blob/764193013f84cfe4f82d7d1f1739c4561ef65860/lib/src/main/scala /spinal/lib/eda/altera/QSys.scala#L12>`_
3 months ago
User avatar tsy0123

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Libraries/EDA/altera/qsysify
  3. Chinese (Simplified)
Adding new interface support
添加新的接口支持
3 months ago
User avatar tsy0123

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Libraries/EDA/altera/qsysify
  3. Chinese (Simplified)
AvalonMM / APB3
阿瓦隆AvalonMM / APB3
3 months ago
User avatar tsy0123

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Libraries/EDA/altera/qsysify
  3. Chinese (Simplified)
Because QSys require some information that are not specified in the SpinalHDL hardware specification, some tags should be added to interface:
由于 QSys 需要一些 SpinalHDL 硬件规范中未指定的信息，因此应在接口中添加一些标签：
3 months ago
User avatar tsy0123

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Libraries/EDA/altera/qsysify
  3. Chinese (Simplified)
tags
标签
3 months ago
User avatar tsy0123

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Libraries/EDA/altera/qsysify
  3. Chinese (Simplified)
The following ``main`` will generate the Verilog and the QSys TCL script with io.bus as an AvalonMM and io.uart as a conduit :
以下“下面的 ``main”`` 将生成 Verilog 和 和QSys TCL 脚本，其中 io.bus 将作为 AvalonMM总线，io.uart 作为管道导线：
3 months ago
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