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Overview

Project website spinalhdl.github.io/SpinalDoc-RTD
Instructions for translators

SpinalHDL的使用说明
Project maintainers User avatar Readon User avatar SpinalHDL-CN User avatar tsy0123
Translation license Creative Commons Zero v1.0 Universal
Translation process
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  • Translation suggestions can be made.
  • Translations are reviewed by dedicated reviewers.
  • Any authenticated user can contribute.
  • The translation uses bilingual files.
Source code repository git@github.com:SpinalHDL-CN/SpinalDoc-RTD.git
Repository branch master
Last remote commit don't fail on check link 29e24f116
Dolu1990 authored 2 weeks ago
Last commit in Weblate Translated using Weblate (Chinese (Simplified)) 9f25c5b8c
User avatar tsy0123 authored 3 months ago
Weblate repository https://hosted.weblate.org/git/spinaldoc-rtd/index/
File mask source/locale/*/LC_MESSAGES/SpinalHDL/Sequential logic/registers.po
3 weeks ago

String statistics

Strings percent Hosted strings Words percent Hosted words Characters percent Hosted characters
Total 74 1,234 7,610
Source 37 617 3,805
Approved 50% 37 50% 617 50% 3,805
Waiting for review 0% 0 0% 0 0% 0
Translated 100% 74 100% 1,234 100% 7,610
Needs editing 0% 0 0% 0 0% 0
Read-only 50% 37 50% 617 50% 3,805
Failing checks 5% 4 7% 88 7% 560
Strings with suggestions 1% 1 7% 91 7% 544
Untranslated strings 0% 0 0% 0 0% 0
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User avatar None

Changes committed

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. Chinese (Simplified)
Changes committed 3 months ago
User avatar tsy0123

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. Chinese (Simplified)
Sometimes it is useful to transform an existing wire into a register. For instance, when you are using a Bundle, if you want some outputs of the bundle to be registers, you might prefer to write ``io.myBundle.PORT := newValue`` without declaring registers with ``val PORT = Reg(...)`` and connecting their output to the port with ``io.myBundle.PORT := PORT``. To do this, you just need to use ``.setAsReg()`` on the ports you want to control as registers:
有时将现有的连线转换为寄存器很有用。例如，当您使用线束（Bundle）时，如果您希望线束的某些输出成为寄存器，您可能更愿意编写 ``io.myBundle.PORT := newValue`` 而不用 ``val PORT = Reg( ...)`` 并将其输出连接到带有 ``io.myBundle.PORT := PORT`` 的端口。为此，您只需在要实例化为寄存器的端口上使用 ``.setAsReg()``：
3 months ago
User avatar tsy0123

Contributor joined

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. Chinese (Simplified)
Contributor joined 3 months ago
User avatar None

Resource updated

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. English
The “source/locale/gettext/SpinalHDL/Sequential logic/registers.pot” file was changed. 4 months ago
User avatar Readon

Changes committed

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. Chinese (Simplified)
Changes committed 4 months ago
User avatar Readon

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. Chinese (Simplified)
In the example above, the wire is defined in the ``io`` Bundle, in the same clock domain as the component. Even if ``io.apb.PADDR.setAsReg()`` was written in a ``ClockingArea`` with a different clock domain, the register would use the clock domain of the component and not the one of the ``ClockingArea``.
在上面的示例中，线路在“io”捆绑包 ``io`` 线束中定义，与组件位于同一时钟域中。即使“ ``io.apb.PADDR.setAsReg()”写入`` 这条代码写在具有不同时钟域的“ ``ClockingArea”`` 中，寄存器也将使用组件的时钟域，而不是“ ``ClockingArea”`` 的时钟域`。
4 months ago
User avatar Readon

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. Chinese (Simplified)
The register is created in the clock domain of the wire, and does not depend on the place where ``.setAsReg()`` is used.
该寄存器是在线路/信号的时钟域中创建的，并且不依赖于使用 ``.setAsReg()`` 的位置。
4 months ago
User avatar Readon

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. Chinese (Simplified)
The register is created in the clock domain of the wire, and does not depend on the place where ``.setAsReg()`` is used.
该寄存器是在线路的时钟域中创建的，并且不依赖于使用 ``.setAsReg()`` 的位置。
4 months ago
User avatar Readon

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. Chinese (Simplified)
Notice in the code above that you can also specify an initialization value.
请注意，在上面的代码中，您还可以指定初始化值。
4 months ago
User avatar Readon

Translation approved

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. Chinese (Simplified)
Sometimes it is useful to transform an existing wire into a register. For instance, when you are using a Bundle, if you want some outputs of the bundle to be registers, you might prefer to write ``io.myBundle.PORT := newValue`` without declaring registers with ``val PORT = Reg(...)`` and connecting their output to the port with ``io.myBundle.PORT := PORT``. To do this, you just need to use ``.setAsReg()`` on the ports you want to control as registers:
有时将现有的连线转换为寄存器很有用。例如，当您使用线束（Bundle）时，如果您希望线束的某些输出成为寄存器，您可能更愿意编写 ``io.myBundle.PORT := newValue`` 而不用 ``val PORT = Reg( ...)`` 并将其输出连接到带有``io.myBundle.PORT := PORT`` 的端口。为此，您只需在要控制实例化为寄存器的端口上使用 ``.setAsReg()``：
4 months ago
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