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Overview

Project website spinalhdl.github.io/SpinalDoc-RTD
Instructions for translators

SpinalHDL的使用说明
Project maintainers User avatar Readon User avatar SpinalHDL-CN User avatar tsy0123
Translation license Creative Commons Zero v1.0 Universal
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  • The translation uses bilingual files.
Source code repository git@github.com:SpinalHDL-CN/SpinalDoc-RTD.git
Repository branch master
Last remote commit update .pot files 0dd5fe26e
GiHub Action Bot authored a week ago
Last commit in Weblate Translated using Weblate (Chinese (Simplified)) 9f25c5b8c
User avatar tsy0123 authored 4 months ago
Weblate repository https://hosted.weblate.org/git/spinaldoc-rtd/index/
File mask source/locale/*/LC_MESSAGES/SpinalHDL/Sequential logic/registers.po
Translation file Download source/locale/gettext/SpinalHDL/Sequential logic/registers.pot
Last change None
Last author None
a week ago

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Total 37 617 3,805
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Translated 100% 37 100% 617 100% 3,805
Needs editing 0% 0 0% 0 0% 0
Read-only 100% 37 100% 617 100% 3,805
Failing checks 2% 1 12% 76 11% 455
Strings with suggestions 0% 0 0% 0 0% 0
Untranslated strings 0% 0 0% 0 0% 0
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Resource updated

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. English
The “source/locale/gettext/SpinalHDL/Sequential logic/registers.pot” file was changed. 4 months ago
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Resource updated

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. English
The “source/locale/gettext/SpinalHDL/Sequential logic/registers.pot” file was changed. 5 months ago
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Resource updated

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. English
File “source/locale/template/SpinalHDL/Sequential logic/registers.pot” was added. 5 months ago
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String updated in the repository

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. English
In the example above, the wire is defined in the ``io`` Bundle, in the same clock domain as the component. Even if ``io.apb.PADDR.setAsReg()`` was written in a ``ClockingArea`` with a different clock domain, the register would use the clock domain of the component and not the one of the ``ClockingArea``.
In the example above, the wire is defined in the ``io`` Bundle, in the same clock domain as the component. Even if ``io.apb.PADDR.setAsReg()`` was written in a ``ClockingArea`` with a different clock domain, the register would use the clock domain of the component and not the one of the ``ClockingArea``.
5 months ago
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String updated in the repository

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. English
The register is created in the clock domain of the wire, and does not depend on the place where ``.setAsReg()`` is used.
The register is created in the clock domain of the wire, and does not depend on the place where ``.setAsReg()`` is used.
5 months ago
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String updated in the repository

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. English
Notice in the code above that you can also specify an initialization value.
Notice in the code above that you can also specify an initialization value.
5 months ago
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String updated in the repository

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. English
Sometimes it is useful to transform an existing wire into a register. For instance, when you are using a Bundle, if you want some outputs of the bundle to be registers, you might prefer to write ``io.myBundle.PORT := newValue`` without declaring registers with ``val PORT = Reg(...)`` and connecting their output to the port with ``io.myBundle.PORT := PORT``. To do this, you just need to use ``.setAsReg()`` on the ports you want to control as registers:
Sometimes it is useful to transform an existing wire into a register. For instance, when you are using a Bundle, if you want some outputs of the bundle to be registers, you might prefer to write ``io.myBundle.PORT := newValue`` without declaring registers with ``val PORT = Reg(...)`` and connecting their output to the port with ``io.myBundle.PORT := PORT``. To do this, you just need to use ``.setAsReg()`` on the ports you want to control as registers:
5 months ago
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String updated in the repository

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. English
Transforming a wire into a register
Transforming a wire into a register
5 months ago
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String updated in the repository

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. English
In case where the initialization must be deferred since the init value is not known, use a function as in the example below.
In case where the initialization must be deferred since the init value is not known, use a function as in the example below.
5 months ago
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String updated in the repository

  1. SpinalDoc-RTD
  2. SpinalHDL/Sequential logic/registers
  3. English
Initialization can be done with the ``init`` method as usual, which can be combined with the ``foreach`` iteration on the registers.
Initialization can be done with the ``init`` method as usual, which can be combined with the ``foreach`` iteration on the registers.
5 months ago
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