KiCad EDA/v8 — Japanese @ Hosted Weblate: ### Top-level Clauses (version <number>) (rule <rule_name> <rule

Translation

English

### Top-level Clauses

(version <number>)

(rule <rule_name> <rule_clause> ...)

 

### Rule Clauses

(constraint <constraint_type> ...)

(condition "<expression>")

(layer "<layer_name>")

(severity <severity_name>)

 

### Constraints

| Constraint type | Argument type | Description |
|---------------------------|-----------------------------------------------------------------------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| `annular_width` | min/opt/max | Checks the width of annular rings on vias. |
| `assertion` | "<expression>" | Checks the given expression. |
| `clearance` | min | Specifies the **electrical** clearance between copper objects of different nets. (See `physical_clearance` if you wish to specify clearance between objects regardless of net.) To allow copper objects to overlap (collide), create a `clearance` constraint with the `min` value less than zero (for example, `-1`). |
| `courtyard_clearance` | min | Checks the clearance between footprint courtyards and generates an error if any two courtyards are closer than the `min` distance. If a footprint does not have a courtyard shape, no errors will be generated from this constraint. |
| `diff_pair_gap` | min/opt/max | Checks the gap between coupled tracks in a differential pair. Coupled tracks are segments that are parallel to each other. Differential pair gap is not tested on uncoupled portions of a differential pair (for example, the fanout from a component). |
| `diff_pair_uncoupled` | max | Checks the distance that a differential pair track is routed uncoupled from the other polarity track in the pair (for example, where the pair fans out from a component, or becomes uncoupled to pass around another object such as a via). |
| `disallow` | `track` `via` `micro_via` `buried_via` `pad` `zone` `text` `graphic` `hole` `footprint` | Specify one or more object types to disallow, separated by spaces. For example, `(constraint disallow track)` or `(constraint disallow track via pad)`. If an object of this type matches the rule condition, a DRC error will be created. This constraint is essentially the same as a keepout rule area, but can be used to create more specific keepout restrictions. |
| `edge_clearance` | min/opt/max | Checks the clearance between objects and the board edge. This can also be thought of as the "milling tolerance" as the board edge will include all graphical items on the `Edge.Cuts` layer as well as any *oval* pad holes. (See `physical_hole_clearance` for the drilling tolerance.) |
| `length` | min/max | Checks the total routed length for the nets that match the rule condition and generates an error for each net that is below the `min` value (if specified) or above the `max` value (if specified) of the constraint. |
| `hole` | min/max | Checks the size (diameter) of a drilled hole in a pad or via. For oval holes, the smaller (minor) diameter will be tested against the `min` value (if specified) and the larger (major) diameter will be tested against the `max` value (if specified). |
| `hole_clearance` | min | Checks the clearance between a drilled hole in a pad or via and copper objects on a different net. The clearance is measured from the diameter of the hole, not its center. |
| `hole_to_hole` | min | Checks the clearance between mechanically-drilled holes in pads and vias. The clearance is measured between the diameters of the holes, not between their centers. This constraint is soley for the protection of drill bits. The clearance between **laser-drilled** (microvias) and other non-mechanically-drilled holes is not checked, nor is the clearance between **milled** (oval-shaped) and other non-mechanically-drilled holes. |
| `physical_clearance` | min | Checks the clearance between two objects on a given layer (including non-copper layers). While this can perform more general-purpose checks than `clearance`, it is much slower. Use `clearance` where possible. |
| `physical_hole_clearance` | min | Checks the clearance between a drilled hole in a pad or via and another object, regardless of net. The clearance is measured from the diameter of the hole, not its center. This can also be thought of as the "drilling tolerance" as it only includes **round** holes (see `edge_clearance` for the milling tolerance). |
| `silk_clearance` | min/opt/max | Checks the clearance between objects on silkscreen layers and other objects. |
| `skew` | max | Checks the total skew for the nets that match the rule condition, that is, the difference between the length of each net and the average of all the lengths of each net that is matched by the rule. If the absolute value of the difference between that average and the length of any one net is above the constraint `max` value, an error will be generated. |
| `thermal_relief_gap` | min | Specifies the width of the gap between a pad and a zone with a thermal-relief connection. |
| `thermal_spoke_width` | opt | Specifies the width of the spokes connecting a pad to a zone with a thermal-relief connection. |
| `track_width` | min/opt/max | Checks the width of track and arc segments. An error will be generated for each segment that has a width below the `min` value (if specified) or above the `max` value (if specified). |
| `via_count` | max | Counts the number of vias on every net matched by the rule condition. If that number exceeds the constraint `max` value on any matched net, an error will be generated for that net. |
| `zone_connection` | `solid` `thermal_reliefs` `none` | Specifies the connection to be made between a zone and a pad. |

### Items

* `A`    _the first (or only) item under test_
* `B`    _the second item under test (for binary tests)_
* `L`    _the layer currently under test_

 

### Severity Names

* warning
* error
* exclusion
* ignore

 

### Examples

(version 1)

(rule HV
(constraint clearance (min 1.5mm))
(condition "A.NetClass == 'HV'"))

(rule HV
(layer outer)
(constraint clearance (min 1.5mm))
(condition "A.NetClass == 'HV'"))

(rule HV_HV
# wider clearance between HV tracks
(constraint clearance (min "1.5mm + 2.0mm"))
(condition "A.NetClass == 'HV' && B.NetClass == 'HV'"))

(rule HV_unshielded
(constraint clearance (min 2mm))
(condition "A.NetClass == 'HV' && !A.enclosedByArea('Shield*')"))

(rule heavy_thermals
(constraint thermal_spoke_width (min 0.5mm))
(condition "A.NetClass == 'HV'"))
 

### Notes

Version clause must be the first clause. It indicates the syntax version of the file so that
future rules parsers can perform automatic updates. It should be
set to "1".

Rules should be ordered by specificity. Later rules take
precedence over earlier rules; once a matching rule is found
no further rules will be checked.

Use Ctrl+/ to comment or uncomment line(s).
 

### Expression functions

All function parameters support simple wildcards (`*` and `?`).
 

A.intersectsCourtyard('<footprint_refdes>')
True if any part of `A` lies within the given footprint's principal courtyard.
 

A.intersectsFrontCourtyard('<footprint_refdes>')
True if any part of `A` lies within the given footprint's front courtyard.
 

A.intersectsBackCourtyard('<footprint_refdes>')
True if any part of `A` lies within the given footprint's back courtyard.
 

A.intersectsArea('<zone_name>')
True if any part of `A` lies within the given zone's outline.
 

A.enclosedByArea('<zone_name>')
True if all of `A` lies within the given zone's outline.

NB: this is potentially a more expensive call than `intersectsArea()`. Use `intersectsArea()`
where possible.
 

A.getField('<field_name>')
The value of the given field. Only footprints have fields, so a field is only returned if
`A` is a footprint.
 

A.isPlated()
True if `A` has a hole which is plated.
 

A.inDiffPair('<net_name>')
True if `A` has a net that is part of the specified differential pair.
`<net_name>` is the base name of the differential pair. For example, `inDiffPair('/CLK')`
matches items in the `/CLK_P` and `/CLK_N` nets.
 

AB.isCoupledDiffPair()
True if `A` and `B` are members of the same diff pair.
 

A.memberOfGroup('<group_name>')
True if `A` is a member of the given group. The name can contain wildcards.
Includes nested membership.
 

A.memberOfFootprint('<footprint_reference>|<footprint_id>')
True if `A` is a member of a footprint matching the given reference designator or footprint
ID. The parameter can contain wildcards.

NB: If matching against a footprint ID is desired, the parameter must contain a ':'.
 

A.memberOfSheet('<sheet_path>')
True if `A` is a member of the given schematic sheet. The sheet path can contain wildcards.
 

A.existsOnLayer('<layer_name>')
True if `A` exists on the given layer. The layer name can be
either the name assigned in Board Setup > Board Editor Layers or
the canonical name (ie: `F.Cu`).

NB: this returns true if `A` is on the given layer, independently
of whether or not the rule is being evaluated for that layer.
For the latter use a `(layer "layer_name")` clause in the rule.
 

### More Examples

(rule "copper keepout"
(constraint disallow track via zone)
(condition "A.intersectsArea('zone3')"))

(rule "BGA neckdown"
(constraint track_width (min 0.2mm) (opt 0.25mm))
(constraint clearance (min 0.05mm) (opt 0.08mm))
(condition "A.intersectsCourtyard('U3')"))

# prevent silk over tented vias
(rule silk_over_via
(constraint silk_clearance (min 0.2mm))
(condition "A.Type == '*Text' && B.Type == 'Via'"))

(rule "Distance between Vias of Different Nets"
(constraint hole_to_hole (min 0.254mm))
(condition "A.Type == 'Via' && B.Type == 'Via' && A.Net != B.Net"))

(rule "Clearance between Pads of Different Nets"
(constraint clearance (min 3.0mm))
(condition "A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B.Net"))

(rule "Via Hole to Track Clearance"
(constraint hole_clearance (min 0.254mm))
(condition "A.Type == 'Via' && B.Type == 'Track'"))

(rule "Pad to Track Clearance"
(constraint clearance (min 0.2mm))
(condition "A.Type == 'Pad' && B.Type == 'Track'"))

(rule "clearance-to-1mm-cutout"
(constraint edge_clearance (min 0.8mm))
(condition "A.Layer == 'Edge.Cuts' && A.Line_Width == 1.0mm"))

(rule "Max Drill Hole Size Mechanical"
(constraint hole_size (max 6.3mm))
(condition "A.Pad_Type == 'NPTH, mechanical'"))

(rule "Max Drill Hole Size PTH"
(constraint hole_size (max 6.35mm))
(condition "A.Pad_Type == 'Through-hole'"))

# Specify an optimal gap for a particular diff-pair
(rule "dp clock gap"
(constraint diff_pair_gap (opt "0.8mm"))
(condition "A.inDiffPair('/CLK')"))

# Specify a larger clearance around any diff-pair
(rule "dp clearance"
(constraint clearance (min "1.5mm"))
(condition "A.inDiffPair('*') && !AB.isCoupledDiffPair()"))

# Don't use thermal reliefs on heatsink pads
(rule heat_sink_pad
(constraint zone_connection solid)
(condition "A.Fabrication_Property == 'Heatsink pad'"))

# Require all four thermal relief spokes to connect to parent zone
(rule fully_spoked_pads
(constraint min_resolved_spokes 4))

# Set thermal relief gap & spoke width for all zones
(rule defined_relief
(constraint thermal_relief_gap (min 10mil))
(constraint thermal_spoke_width (min 12mil)))

# Override thermal relief gap & spoke width for GND and PWR zones
(rule defined_relief_pwr
(constraint thermal_relief_gap (min 10mil))
(constraint thermal_spoke_width (min 12mil))
(condition "A.Name == 'zone_GND' || A.Name == 'zone_PWR'"))

# Prevent solder wicking from SMD pads
(rule holes_in_pads
(constraint physical_hole_clearance (min 0.2mm))
(condition "B.Pad_Type == 'SMD'"))

# Disallow solder mask margin overrides
(rule "disallow solder mask margin overrides"
(constraint assertion "A.Soldermask_Margin_Override == 0mm")
(condition "A.Type == 'Pad'"))

# Enforce a mechanical clearance between components and board edge
(rule front_mechanical_board_edge_clearance
(layer "F.Courtyard")
(constraint physical_clearance (min 3mm))
(condition "B.Layer == 'Edge.Cuts'"))

# Check current-carrying capacity
(rule high-current
(constraint track_width (min 1.0mm))
(constraint connection_width (min 0.8mm))
(condition "A.NetClass == 'Power'"))

# Separate drill bit and milling cutter size constraints
(rule "Plated through-hole size"
(constraint hole_size (min 0.2mm) (max 6.35mm))
(condition "A.isPlated() && A.Hole_Size_X == A.Hole_Size_Y"))

(rule "Plated slot size"
(constraint hole_size (min 0.5mm))
(condition "A.isPlated() && A.Hole_Size_X != A.Hole_Size_Y"))

### Documentation

For the full documentation see [https://docs.kicad.org](https://docs.kicad.org/GetMajorMinorVersion/en/pcbnew/pcbnew.html#custom_design_rules).

Japanese

### トップレベルの句

(version <number>)

(rule <rule_name> <rule_clause> ...)

### ルール句

(constraint <constraint_type> ...)

(condition "<expression>")

(layer "<layer_name>")

(severity <severity_name>)

### 制約

| 制約タイプ | 引数タイプ | 説明 |
|---------------------------|------------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| `annular_width` | min/opt/max | Checks the width of annular rings on vias. |
| `clearance` | min | Specifies the **electrical** clearance between copper objects of different nets. (See `physical_clearance` if you wish to specify clearance between objects regardless of net.) To allow copper objects to overlap (collide), create a `clearance` constraint with the `min` value less than zero (for example, `-1`). |
| `courtyard_clearance` | min | Checks the clearance between footprint courtyards and generates an error if any two courtyards are closer than the `min` distance. If a footprint does not have a courtyard shape, no errors will be generated from this constraint. |
| `diff_pair_gap` | min/opt/max | Checks the gap between coupled tracks in a differential pair. Coupled tracks are segments that are parallel to each other. Differential pair gap is not tested on uncoupled portions of a differential pair (for example, the fanout from a component). |
| `diff_pair_uncoupled` | max | Checks the distance that a differential pair track is routed uncoupled from the other polarity track in the pair (for example, where the pair fans out from a component, or becomes uncoupled to pass around another object such as a via). |
| `disallow` | `track` `via` `micro_via` `buried_via` `pad` `zone` `text` `graphic` `hole` `footprint` | Specify one or more object types to disallow, separated by spaces. For example, `(constraint disallow track)` or `(constraint disallow track via pad)`. If an object of this type matches the rule condition, a DRC error will be created. This constraint is essentially the same as a keepout rule area, but can be used to create more specific keepout restrictions. |
| `edge_clearance` | min/opt/max | Checks the clearance between objects and the board edge. This can also be thought of as the "milling tolerance" as the board edge will include all graphical items on the `Edge.Cuts` layer as well as any *oval* pad holes. (See `physical_hole_clearance` for the drilling tolerance.) |
| `length` | min/max | Checks the total routed length for the nets that match the rule condition and generates an error for each net that is below the `min` value (if specified) or above the `max` value (if specified) of the constraint. |
| `hole` | min/max | Checks the size (diameter) of a drilled hole in a pad or via. For oval holes, the smaller (minor) diameter will be tested against the `min` value (if specified) and the larger (major) diameter will be tested against the `max` value (if specified). |
| `hole_clearance` | min | Checks the clearance between a drilled hole in a pad or via and copper objects on a different net. The clearance is measured from the diameter of the hole, not its center. |
| `hole_to_hole` | min | Checks the clearance between mechanically-drilled holes in pads and vias. The clearance is measured between the diameters of the holes, not between their centers. This constraint is soley for the protection of drill bits. The clearance between **laser-drilled** (microvias) and other non-mechanically-drilled holes is not checked, nor is the clearance between **milled** (oval-shaped) and other non-mechanically-drilled holes. |
| `physical_clearance` | min | Checks the clearance between two objects on a given layer (including non-copper layers). While this can perform more general-purpose checks than `clearance`, it is much slower. Use `clearance` where possible. |
| `physical_hole_clearance` | min | Checks the clearance between a drilled hole in a pad or via and another object, regardless of net. The clearance is measured from the diameter of the hole, not its center. This can also be thought of as the "drilling tolerance" as it only includes **round** holes (see `edge_clearance` for the milling tolerance). |
| `silk_clearance` | min/opt/max | Checks the clearance between objects on silkscreen layers and other objects. |
| `skew` | max | Checks the total skew for the nets that match the rule condition, that is, the difference between the length of each net and the average of all the lengths of each net that is matched by the rule. If the absolute value of the difference between that average and the length of any one net is above the constraint `max` value, an error will be generated. |
| `thermal_relief_gap` | min | Specifies the width of the gap between a pad and a zone with a thermal-relief connection. |
| `thermal_spoke_width` | opt | Specifies the width of the spokes connecting a pad to a zone with a thermal-relief connection. |
| `track_width` | min/opt/max | Checks the width of track and arc segments. An error will be generated for each segment that has a width below the `min` value (if specified) or above the `max` value (if specified). |
| `via_count` | max | Counts the number of vias on every net matched by the rule condition. If that number exceeds the constraint `max` value on any matched net, an error will be generated for that net. |
| `zone_connection` | `solid` `thermal_reliefs` `none` | Specifies the connection to be made between a zone and a pad. |

### アイテム

* `A` &nbsp;&nbsp; _評価の初めの(もしくは唯一の)アイテム_
 * `B` &nbsp;&nbsp; _評価の２つ目のアイテム(バイナリテスト用)_
 * `L` &nbsp;&nbsp; _評価の現在のレイヤー_

### 深刻度名

* warning
 * error
 * exclusion
 * ignore

### 例

(version 1)

(rule HV
       (constraint clearance (min 1.5mm))
       (condition "A.NetClass == 'HV'"))

(rule HV
       (layer outer)
       (constraint clearance (min 1.5mm))
       (condition "A.NetClass == 'HV'"))

(rule HV_HV
       # wider clearance between HV tracks
       (constraint clearance (min "1.5mm + 2.0mm"))
       (condition "A.NetClass == 'HV' && B.NetClass == 'HV'"))

(rule HV_unshielded
       (constraint clearance (min 2mm))
       (condition "A.NetClass == 'HV' && !A.enclosedByArea('Shield*')"))

(rule heavy_thermals
 (constraint thermal_spoke_width (min 0.5mm))
 (condition "A.NetClass == 'HV'"))

### 注

Version句は最初の句でなければなりません。  これはファイルの文法のバージョンを示し、
将来のルールパーサーが自動的にアップデート可能にするためです。
"1"を設定しなければなりません。

ルールは特異性の順に並べます。
後にあるルールは前にあるルールよりも優先されます。
一度マッチするルールが見つかれば、他のルールはチェックされません。

Ctrl+/ の操作で行をコメント化/非コメント化できます。

### 式関数

全ての関数のパラメーターは単純なワイルドカードをサポートします。 (`*` and `?`).

A.intersectsCourtyard('<footprint_refdes>')
`A`のいずれかの部分が与えられたフットプリントのコートヤードの中にある場合、真になります。

A.intersectsFrontCourtyard('<footprint_refdes>')
`A`のいずれかの部分が与えられたフットプリントの表面のコートヤードの中にある場合、真になります。

A.intersectsBackCourtyard('<footprint_refdes>')
`A`のいずれかの部分が与えられたフットプリントの裏面のコートヤードの中にある場合、真になります。

A.intersectsArea('<zone_name>')
`A`のいずれかの部分が与えられたゾーンの中にある場合、真になります。

A.enclosedByArea('<zone_name>')
`A` のすべてが指定されたゾーンのアウトライン内にある場合に真になります。

注意: これは、`intersectsArea()`よりも高コストな呼び出しになる可能性があります。
可能であれば`intersectsArea()`を使用してください。

A.getField('<field_name>')
指定されたフィールドの値を取得します。 フィールドを持つのはフットプリントのみであるため、
`A`がフットプリントの場合にのみフィールドが返されます。

A.isPlated()
`A`にメッキされた穴が含まれている場合、真になります。

A.inDiffPair('<net_name>')
`A`が与えられた差動ペアのネットに属する場合、真になります。
`<net_name>` は差動ペアのベース名です。例えば、`inDiffPair('CLK')`は
`CKL_P`と`CLK_N`のネットにマッチします。

AB.isCoupledDiffPair()
`A`と`B`が同じ差動ペアに属する場合、真になります。

A.memberOf('<group_name>')
`A`が指定されたグループ(ワイルドカードも使えます)に属する場合、真になります。
ネストされたメンバー関係も含みます。

A.memberOfFootprint('<footprint_reference>')
`A`が指定されたリファレンス指定子に一致するフットプリントのに属する場合は真になります。 
リファレンス指定子にはワイルドカードを含めることができます。

A.memberOfSheet('<sheet_path>')
`A`が指定された回路図シートに属する場合は真になります。シートのパスにはワイルドカードを含めることができます。

A.existsOnLayer('<layer_name>')
`A`が与えられたレイヤー状にある場合、真になります。
レイヤー名は 基板の設定 > 基板編集レイヤー で指定された名前か、
正規化名(例: `F.Cu`)が使えます。

注意: これは、ルールがそのレイヤーに対して評価されているかいないかにかかわらず
`A`がレイヤーにある場合に真を返します。
後者の場合、`(layer "layer_name")`の句をルールの中で使います。

### さらなる例

(rule "copper keepout"
       (constraint disallow track via zone)
       (condition "A.intersectsArea('zone3')"))

(rule "BGA neckdown"
       (constraint track_width (min 0.2mm) (opt 0.25mm))
       (constraint clearance (min 0.05mm) (opt 0.08mm))
       (condition "A.intersectsCourtyard('U3')"))

# テンティングされたビアにシルクがかかるのを防ぐ
    (rule silk_over_via
       (constraint silk_clearance (min 0.2mm))
       (condition "A.Type == '*Text' && B.Type == 'Via'"))

(rule "Distance between Vias of Different Nets"
        (constraint hole_to_hole (min 0.254mm))
        (condition "A.Type == 'Via' && B.Type == 'Via' && A.Net != B.Net"))

(rule "Clearance between Pads of Different Nets"
        (constraint clearance (min 3.0mm))
        (condition "A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B.Net"))

(rule "Via Hole to Track Clearance"
        (constraint hole_clearance (min 0.254mm))
        (condition "A.Type == 'Via' && B.Type == 'Track'"))

(rule "Pad to Track Clearance"
        (constraint clearance (min 0.2mm))
        (condition "A.Type == 'Pad' && B.Type == 'Track'"))

(rule "clearance-to-1mm-cutout"
        (constraint edge_clearance (min 0.8mm))
        (condition "A.Layer == 'Edge.Cuts' && A.Line_Width == 1.0mm"))

(rule "Max Drill Hole Size Mechanical"
        (constraint hole_size (max 6.3mm))
        (condition "A.Pad_Type == 'NPTH, mechanical'"))

(rule "Max Drill Hole Size PTH"
        (constraint hole_size (max 6.35mm))
        (condition "A.Pad_Type == 'Through-hole'"))

# 特定の差動ペアに最適なギャップを指定する
    (rule "dp clock gap"
        (constraint diff_pair_gap (opt "0.8mm"))
        (condition "A.inDiffPair('/CLK')"))

# 差動ペアの周りにより大きなクリアランスを指定する
    (rule "dp clearance"
        (constraint clearance (min "1.5mm"))
        (condition "A.inDiffPair('*') && !AB.isCoupledDiffPair()"))

# ヒートシンクパッド上にサーマルリリーフを使わないようにする
    (rule heat_sink_pad
        (constraint zone_connection solid)
        (condition "A.Fabrication_Property == 'Heatsink pad'"))

# 親のゾーンに接続するためにサーマルリリーフのスポークを4つ全て要求する
    (rule fully_spoked_pads
        (constraint min_resolved_spokes 4))

# 全てのゾーンに対してサーマルリリーフのギャップとスポーク幅を設定する
    (rule defined_relief
        (constraint thermal_relief_gap (min 10mil))
        (constraint thermal_spoke_width (min 12mil)))

# GNDとPWRのゾーンに対してサーマルリリーフギャップとスポーク幅をオーバライドする
    (rule defined_relief_pwr
        (constraint thermal_relief_gap (min 10mil))
        (constraint thermal_spoke_width (min 12mil))
        (condition "A.Name == 'zone_GND' || A.Name == 'zone_PWR'"))

# SMDパッドからハンダが漏れるのを防ぐ
    (rule holes_in_pads
        (constraint physical_hole_clearance (min 0.2mm))
        (condition "B.Pad_Type == 'SMD'"))

# ハンダマスクのマージンの上書きを許可しない
    (rule "disallow solder mask margin overrides"
        (constraint assertion "A.Soldermask_Margin_Override == 0mm")
        (condition "A.Type == 'Pad'"))

# 部品と基板端間の機械的クリアランスを強制する
    (rule front_mechanical_board_edge_clearance
        (layer "F.Courtyard")
        (constraint physical_clearance (min 3mm))
        (condition "B.Layer == 'Edge.Cuts'"))

# 電流容量のチェック
    (rule high-current
        (constraint track_width (min 1.0mm))
        (constraint connection_width (min 0.8mm))
        (condition "A.NetClass == 'Power'"))

# ドリルビットとフライスのそれぞれのサイズ制約
    (rule "Plated through-hole size"
        (constraint hole_size (min 0.2mm) (max 6.35mm))
        (condition "A.isPlated() && A.Hole_Size_X == A.Hole_Size_Y"))

(rule "Plated slot size"
        (constraint hole_size (min 0.5mm))
        (condition "A.isPlated() && A.Hole_Size_X != A.Hole_Size_Y"))

### ドキュメント

ドキュメント全文は以下を参照してください。 [https://docs.kicad.org](https://docs.kicad.org/GetMajorMinorVersion/en/pcbnew/pcbnew.html#custom_design_rules).

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	English	Japanese	Actions
	DRC rules	DRC ルール
	ERROR:	エラー:
	Design rules cannot be added without a project	プロジェクトなしでデザインルールを追加することはできません
	DRC rules:	DRC ルール:
	Check rule syntax	ルールの文法をチェック
	### Top-level Clauses (version <number>) (rule <rule_name> <rule_clause> ...) <br> ### Rule Clauses (constraint <constraint_type> ...) (condition "<expression>") (layer "<layer_name>") (severity <severity_name>) <br> ### Constraints \| Constraint type \| Argument type \| Description \| \|---------------------------\|-----------------------------------------------------------------------------------------------------------------------\|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------\| \| `annular_width` \| min/opt/max \| Checks the width of annular rings on vias.<br> \| \| `assertion` \| "<expression>" \| Checks the given expression.<br> \| \| `clearance` \| min \| Specifies the electrical clearance between copper objects of different nets. (See `physical_clearance` if you wish to specify clearance between objects regardless of net.)<br><br>To allow copper objects to overlap (collide), create a `clearance` constraint with the `min` value less than zero (for example, `-1`).<br> \| \| `courtyard_clearance` \| min \| Checks the clearance between footprint courtyards and generates an error if any two courtyards are closer than the `min` distance. If a footprint does not have a courtyard shape, no errors will be generated from this constraint.<br> \| \| `diff_pair_gap` \| min/opt/max \| Checks the gap between coupled tracks in a differential pair. Coupled tracks are segments that are parallel to each other. Differential pair gap is not tested on uncoupled portions of a differential pair (for example, the fanout from a component).<br> \| \| `diff_pair_uncoupled` \| max \| Checks the distance that a differential pair track is routed uncoupled from the other polarity track in the pair (for example, where the pair fans out from a component, or becomes uncoupled to pass around another object such as a via).<br> \| \| `disallow` \| `track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> \| Specify one or more object types to disallow, separated by spaces. For example, `(constraint disallow track)` or `(constraint disallow track via pad)`. If an object of this type matches the rule condition, a DRC error will be created.<br><br>This constraint is essentially the same as a keepout rule area, but can be used to create more specific keepout restrictions.<br> \| \| `edge_clearance` \| min/opt/max \| Checks the clearance between objects and the board edge.<br><br>This can also be thought of as the "milling tolerance" as the board edge will include all graphical items on the `Edge.Cuts` layer as well as any oval pad holes. (See `physical_hole_clearance` for the drilling tolerance.)<br> \| \| `length` \| min/max \| Checks the total routed length for the nets that match the rule condition and generates an error for each net that is below the `min` value (if specified) or above the `max` value (if specified) of the constraint.<br> \| \| `hole` \| min/max \| Checks the size (diameter) of a drilled hole in a pad or via. For oval holes, the smaller (minor) diameter will be tested against the `min` value (if specified) and the larger (major) diameter will be tested against the `max` value (if specified).<br> \| \| `hole_clearance` \| min \| Checks the clearance between a drilled hole in a pad or via and copper objects on a different net. The clearance is measured from the diameter of the hole, not its center.<br> \| \| `hole_to_hole` \| min \| Checks the clearance between mechanically-drilled holes in pads and vias. The clearance is measured between the diameters of the holes, not between their centers.<br><br>This constraint is soley for the protection of drill bits. The clearance between laser-drilled (microvias) and other non-mechanically-drilled holes is not checked, nor is the clearance between milled (oval-shaped) and other non-mechanically-drilled holes.<br> \| \| `physical_clearance` \| min \| Checks the clearance between two objects on a given layer (including non-copper layers).<br><br>While this can perform more general-purpose checks than `clearance`, it is much slower. Use `clearance` where possible.<br> \| \| `physical_hole_clearance` \| min \| Checks the clearance between a drilled hole in a pad or via and another object, regardless of net. The clearance is measured from the diameter of the hole, not its center.<br><br>This can also be thought of as the "drilling tolerance" as it only includes round holes (see `edge_clearance` for the milling tolerance).<br> \| \| `silk_clearance` \| min/opt/max \| Checks the clearance between objects on silkscreen layers and other objects.<br> \| \| `skew` \| max \| Checks the total skew for the nets that match the rule condition, that is, the difference between the length of each net and the average of all the lengths of each net that is matched by the rule. If the absolute value of the difference between that average and the length of any one net is above the constraint `max` value, an error will be generated.<br> \| \| `thermal_relief_gap` \| min \| Specifies the width of the gap between a pad and a zone with a thermal-relief connection.<br> \| \| `thermal_spoke_width` \| opt \| Specifies the width of the spokes connecting a pad to a zone with a thermal-relief connection.<br> \| \| `track_width` \| min/opt/max \| Checks the width of track and arc segments. An error will be generated for each segment that has a width below the `min` value (if specified) or above the `max` value (if specified).<br> \| \| `via_count` \| max \| Counts the number of vias on every net matched by the rule condition. If that number exceeds the constraint `max` value on any matched net, an error will be generated for that net.<br> \| \| `zone_connection` \| `solid`<br>`thermal_reliefs`<br>`none` \| Specifies the connection to be made between a zone and a pad.<br> \| ### Items * `A`    _the first (or only) item under test_ * `B`    _the second item under test (for binary tests)_ * `L`    _the layer currently under test_ <br> ### Severity Names * warning * error * exclusion * ignore <br> ### Examples (version 1) (rule HV (constraint clearance (min 1.5mm)) (condition "A.NetClass == 'HV'")) (rule HV (layer outer) (constraint clearance (min 1.5mm)) (condition "A.NetClass == 'HV'")) (rule HV_HV # wider clearance between HV tracks (constraint clearance (min "1.5mm + 2.0mm")) (condition "A.NetClass == 'HV' && B.NetClass == 'HV'")) (rule HV_unshielded (constraint clearance (min 2mm)) (condition "A.NetClass == 'HV' && !A.enclosedByArea('Shield')")) (rule heavy_thermals (constraint thermal_spoke_width (min 0.5mm)) (condition "A.NetClass == 'HV'")) <br><br> ### Notes Version clause must be the first clause. It indicates the syntax version of the file so that future rules parsers can perform automatic updates. It should be set to "1". Rules should be ordered by specificity. Later rules take precedence over earlier rules; once a matching rule is found no further rules will be checked. Use Ctrl+/ to comment or uncomment line(s). <br><br><br> ### Expression functions All function parameters support simple wildcards (`` and `?`). <br><br> A.intersectsCourtyard('<footprint_refdes>') True if any part of `A` lies within the given footprint's principal courtyard. <br><br> A.intersectsFrontCourtyard('<footprint_refdes>') True if any part of `A` lies within the given footprint's front courtyard. <br><br> A.intersectsBackCourtyard('<footprint_refdes>') True if any part of `A` lies within the given footprint's back courtyard. <br><br> A.intersectsArea('<zone_name>') True if any part of `A` lies within the given zone's outline. <br><br> A.enclosedByArea('<zone_name>') True if all of `A` lies within the given zone's outline. NB: this is potentially a more expensive call than `intersectsArea()`. Use `intersectsArea()` where possible. <br><br> A.getField('<field_name>') The value of the given field. Only footprints have fields, so a field is only returned if `A` is a footprint. <br><br> A.isPlated() True if `A` has a hole which is plated. <br><br> A.inDiffPair('<net_name>') True if `A` has a net that is part of the specified differential pair. `<net_name>` is the base name of the differential pair. For example, `inDiffPair('/CLK')` matches items in the `/CLK_P` and `/CLK_N` nets. <br><br> AB.isCoupledDiffPair() True if `A` and `B` are members of the same diff pair. <br><br> A.memberOfGroup('<group_name>') True if `A` is a member of the given group. The name can contain wildcards. Includes nested membership. <br><br> A.memberOfFootprint('<footprint_reference>\|<footprint_id>') True if `A` is a member of a footprint matching the given reference designator or footprint ID. The parameter can contain wildcards. NB: If matching against a footprint ID is desired, the parameter must contain a ':'. <br><br> A.memberOfSheet('<sheet_path>') True if `A` is a member of the given schematic sheet. The sheet path can contain wildcards. <br><br> A.existsOnLayer('<layer_name>') True if `A` exists on the given layer. The layer name can be either the name assigned in Board Setup > Board Editor Layers or the canonical name (ie: `F.Cu`). NB: this returns true if `A` is on the given layer, independently of whether or not the rule is being evaluated for that layer. For the latter use a `(layer "layer_name")` clause in the rule. <br><br> ### More Examples (rule "copper keepout" (constraint disallow track via zone) (condition "A.intersectsArea('zone3')")) (rule "BGA neckdown" (constraint track_width (min 0.2mm) (opt 0.25mm)) (constraint clearance (min 0.05mm) (opt 0.08mm)) (condition "A.intersectsCourtyard('U3')")) # prevent silk over tented vias (rule silk_over_via (constraint silk_clearance (min 0.2mm)) (condition "A.Type == 'Text' && B.Type == 'Via'")) (rule "Distance between Vias of Different Nets" (constraint hole_to_hole (min 0.254mm)) (condition "A.Type == 'Via' && B.Type == 'Via' && A.Net != B.Net")) (rule "Clearance between Pads of Different Nets" (constraint clearance (min 3.0mm)) (condition "A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B.Net")) (rule "Via Hole to Track Clearance" (constraint hole_clearance (min 0.254mm)) (condition "A.Type == 'Via' && B.Type == 'Track'")) (rule "Pad to Track Clearance" (constraint clearance (min 0.2mm)) (condition "A.Type == 'Pad' && B.Type == 'Track'")) (rule "clearance-to-1mm-cutout" (constraint edge_clearance (min 0.8mm)) (condition "A.Layer == 'Edge.Cuts' && A.Line_Width == 1.0mm")) (rule "Max Drill Hole Size Mechanical" (constraint hole_size (max 6.3mm)) (condition "A.Pad_Type == 'NPTH, mechanical'")) (rule "Max Drill Hole Size PTH" (constraint hole_size (max 6.35mm)) (condition "A.Pad_Type == 'Through-hole'")) # Specify an optimal gap for a particular diff-pair (rule "dp clock gap" (constraint diff_pair_gap (opt "0.8mm")) (condition "A.inDiffPair('/CLK')")) # Specify a larger clearance around any diff-pair (rule "dp clearance" (constraint clearance (min "1.5mm")) (condition "A.inDiffPair('') && !AB.isCoupledDiffPair()")) # Don't use thermal reliefs on heatsink pads (rule heat_sink_pad (constraint zone_connection solid) (condition "A.Fabrication_Property == 'Heatsink pad'")) # Require all four thermal relief spokes to connect to parent zone (rule fully_spoked_pads (constraint min_resolved_spokes 4)) # Set thermal relief gap & spoke width for all zones (rule defined_relief (constraint thermal_relief_gap (min 10mil)) (constraint thermal_spoke_width (min 12mil))) # Override thermal relief gap & spoke width for GND and PWR zones (rule defined_relief_pwr (constraint thermal_relief_gap (min 10mil)) (constraint thermal_spoke_width (min 12mil)) (condition "A.Name == 'zone_GND' \|\| A.Name == 'zone_PWR'")) # Prevent solder wicking from SMD pads (rule holes_in_pads (constraint physical_hole_clearance (min 0.2mm)) (condition "B.Pad_Type == 'SMD'")) # Disallow solder mask margin overrides (rule "disallow solder mask margin overrides" (constraint assertion "A.Soldermask_Margin_Override == 0mm") (condition "A.Type == 'Pad'")) # Enforce a mechanical clearance between components and board edge (rule front_mechanical_board_edge_clearance (layer "F.Courtyard") (constraint physical_clearance (min 3mm)) (condition "B.Layer == 'Edge.Cuts'")) # Check current-carrying capacity (rule high-current (constraint track_width (min 1.0mm)) (constraint connection_width (min 0.8mm)) (condition "A.NetClass == 'Power'")) # Separate drill bit and milling cutter size constraints (rule "Plated through-hole size" (constraint hole_size (min 0.2mm) (max 6.35mm)) (condition "A.isPlated() && A.Hole_Size_X == A.Hole_Size_Y")) (rule "Plated slot size" (constraint hole_size (min 0.5mm)) (condition "A.isPlated() && A.Hole_Size_X != A.Hole_Size_Y")) ### Documentation For the full documentation see [https://docs.kicad.org](https://docs.kicad.org/GetMajorMinorVersion/en/pcbnew/pcbnew.html#custom_design_rules).	### トップレベルの句 (version <number>) (rule <rule_name> <rule_clause> ...) <br> ### ルール句 (constraint <constraint_type> ...) (condition "<expression>") (layer "<layer_name>") (severity <severity_name>) <br> ### 制約 \| 制約タイプ \| 引数タイプ \| 説明 \| \|---------------------------\|------------------------------------------------------------------------------------------------------------------------\|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------\| \| `annular_width` \| min/opt/max \| Checks the width of annular rings on vias.<br> \| \| `clearance` \| min \| Specifies the electrical clearance between copper objects of different nets. (See `physical_clearance` if you wish to specify clearance between objects regardless of net.)<br><br>To allow copper objects to overlap (collide), create a `clearance` constraint with the `min` value less than zero (for example, `-1`).<br> \| \| `courtyard_clearance` \| min \| Checks the clearance between footprint courtyards and generates an error if any two courtyards are closer than the `min` distance. If a footprint does not have a courtyard shape, no errors will be generated from this constraint.<br> \| \| `diff_pair_gap` \| min/opt/max \| Checks the gap between coupled tracks in a differential pair. Coupled tracks are segments that are parallel to each other. Differential pair gap is not tested on uncoupled portions of a differential pair (for example, the fanout from a component).<br> \| \| `diff_pair_uncoupled` \| max \| Checks the distance that a differential pair track is routed uncoupled from the other polarity track in the pair (for example, where the pair fans out from a component, or becomes uncoupled to pass around another object such as a via).<br> \| \| `disallow` \| `track`<br>`via`<br>`micro_via`<br>`buried_via`<br>`pad`<br>`zone`<br>`text`<br>`graphic`<br>`hole`<br>`footprint`<br> \| Specify one or more object types to disallow, separated by spaces. For example, `(constraint disallow track)` or `(constraint disallow track via pad)`. If an object of this type matches the rule condition, a DRC error will be created.<br><br>This constraint is essentially the same as a keepout rule area, but can be used to create more specific keepout restrictions.<br> \| \| `edge_clearance` \| min/opt/max \| Checks the clearance between objects and the board edge.<br><br>This can also be thought of as the "milling tolerance" as the board edge will include all graphical items on the `Edge.Cuts` layer as well as any oval pad holes. (See `physical_hole_clearance` for the drilling tolerance.)<br> \| \| `length` \| min/max \| Checks the total routed length for the nets that match the rule condition and generates an error for each net that is below the `min` value (if specified) or above the `max` value (if specified) of the constraint.<br> \| \| `hole` \| min/max \| Checks the size (diameter) of a drilled hole in a pad or via. For oval holes, the smaller (minor) diameter will be tested against the `min` value (if specified) and the larger (major) diameter will be tested against the `max` value (if specified).<br> \| \| `hole_clearance` \| min \| Checks the clearance between a drilled hole in a pad or via and copper objects on a different net. The clearance is measured from the diameter of the hole, not its center.<br> \| \| `hole_to_hole` \| min \| Checks the clearance between mechanically-drilled holes in pads and vias. The clearance is measured between the diameters of the holes, not between their centers.<br><br>This constraint is soley for the protection of drill bits. The clearance between laser-drilled (microvias) and other non-mechanically-drilled holes is not checked, nor is the clearance between milled (oval-shaped) and other non-mechanically-drilled holes.<br> \| \| `physical_clearance` \| min \| Checks the clearance between two objects on a given layer (including non-copper layers).<br><br>While this can perform more general-purpose checks than `clearance`, it is much slower. Use `clearance` where possible.<br> \| \| `physical_hole_clearance` \| min \| Checks the clearance between a drilled hole in a pad or via and another object, regardless of net. The clearance is measured from the diameter of the hole, not its center.<br><br>This can also be thought of as the "drilling tolerance" as it only includes round holes (see `edge_clearance` for the milling tolerance).<br> \| \| `silk_clearance` \| min/opt/max \| Checks the clearance between objects on silkscreen layers and other objects.<br> \| \| `skew` \| max \| Checks the total skew for the nets that match the rule condition, that is, the difference between the length of each net and the average of all the lengths of each net that is matched by the rule. If the absolute value of the difference between that average and the length of any one net is above the constraint `max` value, an error will be generated.<br> \| \| `thermal_relief_gap` \| min \| Specifies the width of the gap between a pad and a zone with a thermal-relief connection.<br> \| \| `thermal_spoke_width` \| opt \| Specifies the width of the spokes connecting a pad to a zone with a thermal-relief connection.<br> \| \| `track_width` \| min/opt/max \| Checks the width of track and arc segments. An error will be generated for each segment that has a width below the `min` value (if specified) or above the `max` value (if specified).<br> \| \| `via_count` \| max \| Counts the number of vias on every net matched by the rule condition. If that number exceeds the constraint `max` value on any matched net, an error will be generated for that net.<br> \| \| `zone_connection` \| `solid`<br>`thermal_reliefs`<br>`none` \| Specifies the connection to be made between a zone and a pad.<br> \| ### アイテム * `A`    _評価の初めの(もしくは唯一の)アイテム_ * `B`    _評価の２つ目のアイテム(バイナリテスト用)_ * `L`    _評価の現在のレイヤー_ <br> ### 深刻度名 * warning * error * exclusion * ignore <br> ### 例 (version 1) (rule HV (constraint clearance (min 1.5mm)) (condition "A.NetClass == 'HV'")) (rule HV (layer outer) (constraint clearance (min 1.5mm)) (condition "A.NetClass == 'HV'")) (rule HV_HV # wider clearance between HV tracks (constraint clearance (min "1.5mm + 2.0mm")) (condition "A.NetClass == 'HV' && B.NetClass == 'HV'")) (rule HV_unshielded (constraint clearance (min 2mm)) (condition "A.NetClass == 'HV' && !A.enclosedByArea('Shield')")) (rule heavy_thermals (constraint thermal_spoke_width (min 0.5mm)) (condition "A.NetClass == 'HV'")) <br><br> ### 注 Version句は最初の句でなければなりません。これはファイルの文法のバージョンを示し、将来のルールパーサーが自動的にアップデート可能にするためです。 "1"を設定しなければなりません。ルールは特異性の順に並べます。後にあるルールは前にあるルールよりも優先されます。一度マッチするルールが見つかれば、他のルールはチェックされません。 Ctrl+/ の操作で行をコメント化/非コメント化できます。 <br><br><br> ### 式関数全ての関数のパラメーターは単純なワイルドカードをサポートします。 (`` and `?`). <br><br> A.intersectsCourtyard('<footprint_refdes>') `A`のいずれかの部分が与えられたフットプリントのコートヤードの中にある場合、真になります。 <br><br> A.intersectsFrontCourtyard('<footprint_refdes>') `A`のいずれかの部分が与えられたフットプリントの表面のコートヤードの中にある場合、真になります。 <br><br> A.intersectsBackCourtyard('<footprint_refdes>') `A`のいずれかの部分が与えられたフットプリントの裏面のコートヤードの中にある場合、真になります。 <br><br> A.intersectsArea('<zone_name>') `A`のいずれかの部分が与えられたゾーンの中にある場合、真になります。 <br><br> A.enclosedByArea('<zone_name>') `A` のすべてが指定されたゾーンのアウトライン内にある場合に真になります。注意: これは、`intersectsArea()`よりも高コストな呼び出しになる可能性があります。可能であれば`intersectsArea()`を使用してください。 <br><br> A.getField('<field_name>') 指定されたフィールドの値を取得します。フィールドを持つのはフットプリントのみであるため、 `A`がフットプリントの場合にのみフィールドが返されます。 <br><br> A.isPlated() `A`にメッキされた穴が含まれている場合、真になります。 <br><br> A.inDiffPair('<net_name>') `A`が与えられた差動ペアのネットに属する場合、真になります。 `<net_name>` は差動ペアのベース名です。例えば、`inDiffPair('CLK')`は `CKL_P`と`CLK_N`のネットにマッチします。 <br><br> AB.isCoupledDiffPair() `A`と`B`が同じ差動ペアに属する場合、真になります。 <br><br> A.memberOf('<group_name>') `A`が指定されたグループ(ワイルドカードも使えます)に属する場合、真になります。ネストされたメンバー関係も含みます。 <br><br> A.memberOfFootprint('<footprint_reference>') `A`が指定されたリファレンス指定子に一致するフットプリントのに属する場合は真になります。リファレンス指定子にはワイルドカードを含めることができます。 <br><br> A.memberOfSheet('<sheet_path>') `A`が指定された回路図シートに属する場合は真になります。シートのパスにはワイルドカードを含めることができます。 <br><br> A.existsOnLayer('<layer_name>') `A`が与えられたレイヤー状にある場合、真になります。レイヤー名は基板の設定 > 基板編集レイヤーで指定された名前か、正規化名(例: `F.Cu`)が使えます。注意: これは、ルールがそのレイヤーに対して評価されているかいないかにかかわらず `A`がレイヤーにある場合に真を返します。後者の場合、`(layer "layer_name")`の句をルールの中で使います。 <br><br> ### さらなる例 (rule "copper keepout" (constraint disallow track via zone) (condition "A.intersectsArea('zone3')")) (rule "BGA neckdown" (constraint track_width (min 0.2mm) (opt 0.25mm)) (constraint clearance (min 0.05mm) (opt 0.08mm)) (condition "A.intersectsCourtyard('U3')")) # テンティングされたビアにシルクがかかるのを防ぐ (rule silk_over_via (constraint silk_clearance (min 0.2mm)) (condition "A.Type == 'Text' && B.Type == 'Via'")) (rule "Distance between Vias of Different Nets" (constraint hole_to_hole (min 0.254mm)) (condition "A.Type == 'Via' && B.Type == 'Via' && A.Net != B.Net")) (rule "Clearance between Pads of Different Nets" (constraint clearance (min 3.0mm)) (condition "A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B.Net")) (rule "Via Hole to Track Clearance" (constraint hole_clearance (min 0.254mm)) (condition "A.Type == 'Via' && B.Type == 'Track'")) (rule "Pad to Track Clearance" (constraint clearance (min 0.2mm)) (condition "A.Type == 'Pad' && B.Type == 'Track'")) (rule "clearance-to-1mm-cutout" (constraint edge_clearance (min 0.8mm)) (condition "A.Layer == 'Edge.Cuts' && A.Line_Width == 1.0mm")) (rule "Max Drill Hole Size Mechanical" (constraint hole_size (max 6.3mm)) (condition "A.Pad_Type == 'NPTH, mechanical'")) (rule "Max Drill Hole Size PTH" (constraint hole_size (max 6.35mm)) (condition "A.Pad_Type == 'Through-hole'")) # 特定の差動ペアに最適なギャップを指定する (rule "dp clock gap" (constraint diff_pair_gap (opt "0.8mm")) (condition "A.inDiffPair('/CLK')")) # 差動ペアの周りにより大きなクリアランスを指定する (rule "dp clearance" (constraint clearance (min "1.5mm")) (condition "A.inDiffPair('') && !AB.isCoupledDiffPair()")) # ヒートシンクパッド上にサーマルリリーフを使わないようにする (rule heat_sink_pad (constraint zone_connection solid) (condition "A.Fabrication_Property == 'Heatsink pad'")) # 親のゾーンに接続するためにサーマルリリーフのスポークを4つ全て要求する (rule fully_spoked_pads (constraint min_resolved_spokes 4)) # 全てのゾーンに対してサーマルリリーフのギャップとスポーク幅を設定する (rule defined_relief (constraint thermal_relief_gap (min 10mil)) (constraint thermal_spoke_width (min 12mil))) # GNDとPWRのゾーンに対してサーマルリリーフギャップとスポーク幅をオーバライドする (rule defined_relief_pwr (constraint thermal_relief_gap (min 10mil)) (constraint thermal_spoke_width (min 12mil)) (condition "A.Name == 'zone_GND' \|\| A.Name == 'zone_PWR'")) # SMDパッドからハンダが漏れるのを防ぐ (rule holes_in_pads (constraint physical_hole_clearance (min 0.2mm)) (condition "B.Pad_Type == 'SMD'")) # ハンダマスクのマージンの上書きを許可しない (rule "disallow solder mask margin overrides" (constraint assertion "A.Soldermask_Margin_Override == 0mm") (condition "A.Type == 'Pad'")) # 部品と基板端間の機械的クリアランスを強制する (rule front_mechanical_board_edge_clearance (layer "F.Courtyard") (constraint physical_clearance (min 3mm)) (condition "B.Layer == 'Edge.Cuts'")) # 電流容量のチェック (rule high-current (constraint track_width (min 1.0mm)) (constraint connection_width (min 0.8mm)) (condition "A.NetClass == 'Power'")) # ドリルビットとフライスのそれぞれのサイズ制約 (rule "Plated through-hole size" (constraint hole_size (min 0.2mm) (max 6.35mm)) (condition "A.isPlated() && A.Hole_Size_X == A.Hole_Size_Y")) (rule "Plated slot size" (constraint hole_size (min 0.5mm)) (condition "A.isPlated() && A.Hole_Size_X != A.Hole_Size_Y")) ### ドキュメントドキュメント全文は以下を参照してください。 [https://docs.kicad.org](https://docs.kicad.org/GetMajorMinorVersion/en/pcbnew/pcbnew.html#custom_design_rules).
	Default properties for round shapes:	円形の形状に対するデフォルト値:
	Edges:	形状:
	Straight lines	直線
	Curved	曲線
	Curve points:	ベジェ曲線の制御点:

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English

Japanese 19803 characters edited Current translation Needs editing

### トップレベルの句

(version <number>)

(rule <rule_name> <rule_clause> ...)

 

### ルール句

(constraint <constraint_type> ...)

(condition "<expression>")

(layer "<layer_name>")

(severity <severity_name>)

 

### 制約

| 制約タイプ | 引数タイプ | 説明 |
|---------------------------|------------------------------------------------------------------------------------------------------------------------|---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
| `annular_width` | min/opt/max | Checks the width of annular rings on vias. |
| `clearance` | min | Specifies the **electrical** clearance between copper objects of different nets. (See `physical_clearance` if you wish to specify clearance between objects regardless of net.) To allow copper objects to overlap (collide), create a `clearance` constraint with the `min` value less than zero (for example, `-1`). |
| `courtyard_clearance` | min | Checks the clearance between footprint courtyards and generates an error if any two courtyards are closer than the `min` distance. If a footprint does not have a courtyard shape, no errors will be generated from this constraint. |
| `diff_pair_gap` | min/opt/max | Checks the gap between coupled tracks in a differential pair. Coupled tracks are segments that are parallel to each other. Differential pair gap is not tested on uncoupled portions of a differential pair (for example, the fanout from a component). |
| `diff_pair_uncoupled` | max | Checks the distance that a differential pair track is routed uncoupled from the other polarity track in the pair (for example, where the pair fans out from a component, or becomes uncoupled to pass around another object such as a via). |
| `disallow` | `track` `via` `micro_via` `buried_via` `pad` `zone` `text` `graphic` `hole` `footprint` | Specify one or more object types to disallow, separated by spaces. For example, `(constraint disallow track)` or `(constraint disallow track via pad)`. If an object of this type matches the rule condition, a DRC error will be created. This constraint is essentially the same as a keepout rule area, but can be used to create more specific keepout restrictions. |
| `edge_clearance` | min/opt/max | Checks the clearance between objects and the board edge. This can also be thought of as the "milling tolerance" as the board edge will include all graphical items on the `Edge.Cuts` layer as well as any *oval* pad holes. (See `physical_hole_clearance` for the drilling tolerance.) |
| `length` | min/max | Checks the total routed length for the nets that match the rule condition and generates an error for each net that is below the `min` value (if specified) or above the `max` value (if specified) of the constraint. |
| `hole` | min/max | Checks the size (diameter) of a drilled hole in a pad or via. For oval holes, the smaller (minor) diameter will be tested against the `min` value (if specified) and the larger (major) diameter will be tested against the `max` value (if specified). |
| `hole_clearance` | min | Checks the clearance between a drilled hole in a pad or via and copper objects on a different net. The clearance is measured from the diameter of the hole, not its center. |
| `hole_to_hole` | min | Checks the clearance between mechanically-drilled holes in pads and vias. The clearance is measured between the diameters of the holes, not between their centers. This constraint is soley for the protection of drill bits. The clearance between **laser-drilled** (microvias) and other non-mechanically-drilled holes is not checked, nor is the clearance between **milled** (oval-shaped) and other non-mechanically-drilled holes. |
| `physical_clearance` | min | Checks the clearance between two objects on a given layer (including non-copper layers). While this can perform more general-purpose checks than `clearance`, it is much slower. Use `clearance` where possible. |
| `physical_hole_clearance` | min | Checks the clearance between a drilled hole in a pad or via and another object, regardless of net. The clearance is measured from the diameter of the hole, not its center. This can also be thought of as the "drilling tolerance" as it only includes **round** holes (see `edge_clearance` for the milling tolerance). |
| `silk_clearance` | min/opt/max | Checks the clearance between objects on silkscreen layers and other objects. |
| `skew` | max | Checks the total skew for the nets that match the rule condition, that is, the difference between the length of each net and the average of all the lengths of each net that is matched by the rule. If the absolute value of the difference between that average and the length of any one net is above the constraint `max` value, an error will be generated. |
| `thermal_relief_gap` | min | Specifies the width of the gap between a pad and a zone with a thermal-relief connection. |
| `thermal_spoke_width` | opt | Specifies the width of the spokes connecting a pad to a zone with a thermal-relief connection. |
| `track_width` | min/opt/max | Checks the width of track and arc segments. An error will be generated for each segment that has a width below the `min` value (if specified) or above the `max` value (if specified). |
| `via_count` | max | Counts the number of vias on every net matched by the rule condition. If that number exceeds the constraint `max` value on any matched net, an error will be generated for that net. |
| `zone_connection` | `solid` `thermal_reliefs` `none` | Specifies the connection to be made between a zone and a pad. |

### アイテム

* `A`    _評価の初めの(もしくは唯一の)アイテム_
* `B`    _評価の２つ目のアイテム(バイナリテスト用)_
* `L`    _評価の現在のレイヤー_

 

### 深刻度名

* warning
* error
* exclusion
* ignore

 

### 例

(version 1)

(rule HV
(constraint clearance (min 1.5mm))
(condition "A.NetClass == 'HV'"))

(rule HV
(layer outer)
(constraint clearance (min 1.5mm))
(condition "A.NetClass == 'HV'"))

(rule HV_HV
# wider clearance between HV tracks
(constraint clearance (min "1.5mm + 2.0mm"))
(condition "A.NetClass == 'HV' && B.NetClass == 'HV'"))

(rule HV_unshielded
(constraint clearance (min 2mm))
(condition "A.NetClass == 'HV' && !A.enclosedByArea('Shield*')"))

(rule heavy_thermals
(constraint thermal_spoke_width (min 0.5mm))
(condition "A.NetClass == 'HV'"))
 

### 注

Version句は最初の句でなければなりません。これはファイルの文法のバージョンを示し、
将来のルールパーサーが自動的にアップデート可能にするためです。
"1"を設定しなければなりません。

ルールは特異性の順に並べます。
後にあるルールは前にあるルールよりも優先されます。
一度マッチするルールが見つかれば、他のルールはチェックされません。

Ctrl+/ の操作で行をコメント化/非コメント化できます。
 

### 式関数

全ての関数のパラメーターは単純なワイルドカードをサポートします。 (`*` and `?`).
 

A.intersectsCourtyard('<footprint_refdes>')
`A`のいずれかの部分が与えられたフットプリントのコートヤードの中にある場合、真になります。
 

A.intersectsFrontCourtyard('<footprint_refdes>')
`A`のいずれかの部分が与えられたフットプリントの表面のコートヤードの中にある場合、真になります。
 

A.intersectsBackCourtyard('<footprint_refdes>')
`A`のいずれかの部分が与えられたフットプリントの裏面のコートヤードの中にある場合、真になります。
 

A.intersectsArea('<zone_name>')
`A`のいずれかの部分が与えられたゾーンの中にある場合、真になります。
 

A.enclosedByArea('<zone_name>')
`A` のすべてが指定されたゾーンのアウトライン内にある場合に真になります。

注意: これは、`intersectsArea()`よりも高コストな呼び出しになる可能性があります。
可能であれば`intersectsArea()`を使用してください。
 

A.getField('<field_name>')
指定されたフィールドの値を取得します。フィールドを持つのはフットプリントのみであるため、
`A`がフットプリントの場合にのみフィールドが返されます。
 

A.isPlated()
`A`にメッキされた穴が含まれている場合、真になります。
 

A.inDiffPair('<net_name>')
`A`が与えられた差動ペアのネットに属する場合、真になります。
`<net_name>` は差動ペアのベース名です。例えば、`inDiffPair('CLK')`は
`CKL_P`と`CLK_N`のネットにマッチします。
 

AB.isCoupledDiffPair()
`A`と`B`が同じ差動ペアに属する場合、真になります。
 

A.memberOf('<group_name>')
`A`が指定されたグループ(ワイルドカードも使えます)に属する場合、真になります。
ネストされたメンバー関係も含みます。
 

A.memberOfFootprint('<footprint_reference>')
`A`が指定されたリファレンス指定子に一致するフットプリントのに属する場合は真になります。
リファレンス指定子にはワイルドカードを含めることができます。
 

A.memberOfSheet('<sheet_path>')
`A`が指定された回路図シートに属する場合は真になります。シートのパスにはワイルドカードを含めることができます。
 

A.existsOnLayer('<layer_name>')
`A`が与えられたレイヤー状にある場合、真になります。
レイヤー名は基板の設定 > 基板編集レイヤーで指定された名前か、
正規化名(例: `F.Cu`)が使えます。

注意: これは、ルールがそのレイヤーに対して評価されているかいないかにかかわらず
`A`がレイヤーにある場合に真を返します。
後者の場合、`(layer "layer_name")`の句をルールの中で使います。
 

### さらなる例

(rule "copper keepout"
(constraint disallow track via zone)
(condition "A.intersectsArea('zone3')"))

(rule "BGA neckdown"
(constraint track_width (min 0.2mm) (opt 0.25mm))
(constraint clearance (min 0.05mm) (opt 0.08mm))
(condition "A.intersectsCourtyard('U3')"))

# テンティングされたビアにシルクがかかるのを防ぐ
(rule silk_over_via
(constraint silk_clearance (min 0.2mm))
(condition "A.Type == '*Text' && B.Type == 'Via'"))

(rule "Distance between Vias of Different Nets"
(constraint hole_to_hole (min 0.254mm))
(condition "A.Type == 'Via' && B.Type == 'Via' && A.Net != B.Net"))

(rule "Clearance between Pads of Different Nets"
(constraint clearance (min 3.0mm))
(condition "A.Type == 'Pad' && B.Type == 'Pad' && A.Net != B.Net"))

(rule "Via Hole to Track Clearance"
(constraint hole_clearance (min 0.254mm))
(condition "A.Type == 'Via' && B.Type == 'Track'"))

(rule "Pad to Track Clearance"
(constraint clearance (min 0.2mm))
(condition "A.Type == 'Pad' && B.Type == 'Track'"))

(rule "clearance-to-1mm-cutout"
(constraint edge_clearance (min 0.8mm))
(condition "A.Layer == 'Edge.Cuts' && A.Line_Width == 1.0mm"))

(rule "Max Drill Hole Size Mechanical"
(constraint hole_size (max 6.3mm))
(condition "A.Pad_Type == 'NPTH, mechanical'"))

(rule "Max Drill Hole Size PTH"
(constraint hole_size (max 6.35mm))
(condition "A.Pad_Type == 'Through-hole'"))

# 特定の差動ペアに最適なギャップを指定する
(rule "dp clock gap"
(constraint diff_pair_gap (opt "0.8mm"))
(condition "A.inDiffPair('/CLK')"))

# 差動ペアの周りにより大きなクリアランスを指定する
(rule "dp clearance"
(constraint clearance (min "1.5mm"))
(condition "A.inDiffPair('*') && !AB.isCoupledDiffPair()"))

# ヒートシンクパッド上にサーマルリリーフを使わないようにする
(rule heat_sink_pad
(constraint zone_connection solid)
(condition "A.Fabrication_Property == 'Heatsink pad'"))

# 親のゾーンに接続するためにサーマルリリーフのスポークを4つ全て要求する
(rule fully_spoked_pads
(constraint min_resolved_spokes 4))

# 全てのゾーンに対してサーマルリリーフのギャップとスポーク幅を設定する
(rule defined_relief
(constraint thermal_relief_gap (min 10mil))
(constraint thermal_spoke_width (min 12mil)))

# GNDとPWRのゾーンに対してサーマルリリーフギャップとスポーク幅をオーバライドする
(rule defined_relief_pwr
(constraint thermal_relief_gap (min 10mil))
(constraint thermal_spoke_width (min 12mil))
(condition "A.Name == 'zone_GND' || A.Name == 'zone_PWR'"))

# SMDパッドからハンダが漏れるのを防ぐ
(rule holes_in_pads
(constraint physical_hole_clearance (min 0.2mm))
(condition "B.Pad_Type == 'SMD'"))

# ハンダマスクのマージンの上書きを許可しない
(rule "disallow solder mask margin overrides"
(constraint assertion "A.Soldermask_Margin_Override == 0mm")
(condition "A.Type == 'Pad'"))

# 部品と基板端間の機械的クリアランスを強制する
(rule front_mechanical_board_edge_clearance
(layer "F.Courtyard")
(constraint physical_clearance (min 3mm))
(condition "B.Layer == 'Edge.Cuts'"))

# 電流容量のチェック
(rule high-current
(constraint track_width (min 1.0mm))
(constraint connection_width (min 0.8mm))
(condition "A.NetClass == 'Power'"))

# ドリルビットとフライスのそれぞれのサイズ制約
(rule "Plated through-hole size"
(constraint hole_size (min 0.2mm) (max 6.35mm))
(condition "A.isPlated() && A.Hole_Size_X == A.Hole_Size_Y"))

(rule "Plated slot size"
(constraint hole_size (min 0.5mm))
(condition "A.isPlated() && A.Hole_Size_X != A.Hole_Size_Y"))

### ドキュメント

ドキュメント全文は以下を参照してください。 [https://docs.kicad.org](https://docs.kicad.org/GetMajorMinorVersion/en/pcbnew/pcbnew.html#custom_design_rules).

3 months ago

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Glossary

English	Japanese
All	すべて	KiCad EDA
Annular	アニュラー	KiCad EDA
Annular rings	アニュラーリング	KiCad EDA
Arc	円弧	KiCad EDA
Area	面積	KiCad EDA
area	エリア	KiCad EDA
assertion	アサーション	KiCad EDA
Automatic	自動	KiCad EDA
Back	裏面	KiCad EDA
bit	ビット	KiCad EDA
bits	ビット	KiCad EDA
Board	基板	KiCad EDA
Board Setup	基板の設定	KiCad EDA
Center	中央	KiCad EDA
center	中心	KiCad EDA
check	チェック	KiCad EDA
Clearance	クリアランス	KiCad EDA
clearance	クリアランス	KiCad EDA
clearance	クリアランス	KiCad EDA
clock	クロック	KiCad EDA
Comment	コメント	KiCad EDA
component	コンポーネント	KiCad EDA
Constraint	制約	KiCad EDA
Constraints	制約	KiCad EDA
Copper	銅	KiCad EDA
Copper Layers	導体レイヤー	KiCad EDA
Courtyards	コートヤード	KiCad EDA
Current	電流	KiCad EDA
Cutout	切り抜き	KiCad EDA
Description	説明	KiCad EDA
Designator	指定子	KiCad EDA
Diameter	直径	KiCad EDA
Diff Pair	差動ペア	KiCad EDA
Differential	差動	KiCad EDA
Distance	距離	KiCad EDA
Drill	ドリル	KiCad EDA
editor	エディター	KiCad EDA
error	エラー	KiCad EDA
Errors	エラー	KiCad EDA
F.Courtyard	基板表面のフットプリントのコートヤード	KiCad EDA
Field	フィールド	KiCad EDA
Fields	フィールド	KiCad EDA
File	ファイル	KiCad EDA
file	ファイル	KiCad EDA
Footprint	フットプリント	KiCad EDA
Footprints	フットプリント	KiCad EDA
Front	表面	KiCad EDA
gap	ギャップ	KiCad EDA
Graphic	グラフィック	KiCad EDA
graphic	グラフィックス	KiCad EDA
Graphical	グラフィカル	KiCad EDA
group	グループ	KiCad EDA
Hole	スルーホール	KiCad EDA
Hole Size	穴サイズ	KiCad EDA
Holes	穴	KiCad EDA
Ignore	無視	KiCad EDA
item	アイテム	KiCad EDA
Items	アイテム	KiCad EDA
Keepout	キープアウト	KiCad EDA
KiCad	KiCad	KiCad EDA
layer	レイヤー	KiCad EDA
layers	レイヤー	KiCad EDA
Length	長さ	KiCad EDA
line	ライン	KiCad EDA
Line	ライン	KiCad EDA
margin	マージン	KiCad EDA
member	メンバー	KiCad EDA
membership	メンバーシップ	KiCad EDA
Name	名前	KiCad EDA
net	ネット	KiCad EDA
NetClass	ネットクラス	KiCad EDA
Nets	ネット	KiCad EDA
No	いいえ	KiCad EDA
None	なし	KiCad EDA
NPTH		KiCad EDA
Number	ピン番号	KiCad EDA
object	オブジェクト	KiCad EDA
Other	その他	KiCad EDA
Outline	アウトライン	KiCad EDA
Oval	長円	KiCad EDA
Overlap	オーバーラップ	KiCad EDA
override	オーバーライド	KiCad EDA
pad	パッド	KiCad EDA
Pads	パッド	KiCad EDA
parameter	パラメーター	KiCad EDA
Parent	親	KiCad EDA
part	パーツ	KiCad EDA
pass	パス	KiCad EDA
Path	パス	KiCad EDA
pcbnew	pcbnew	KiCad EDA
Plated	メッキ	KiCad EDA
Polarity	極性	KiCad EDA
PTH	PTH	KiCad EDA
Reference	リファレンス	KiCad EDA
Reference Designator	リファレンス指定子	KiCad EDA
Restrictions	制限	KiCad EDA
round	ラウンド	KiCad EDA
rule	ルール	KiCad EDA
rule area	ルールエリア	KiCad EDA
Schematic	回路図	KiCad EDA
segment	セグメント	KiCad EDA
set	セット	KiCad EDA
Severity	深刻度	KiCad EDA
Shape	形状	KiCad EDA
sheet	シート	KiCad EDA
Silk	シルク	KiCad EDA
silkscreen	シルクスクリーン	KiCad EDA
Silkscreen	シルクスクリーン	KiCad EDA
silkscreen	シルクスクリーン	KiCad EDA
simple	シンプル	KiCad EDA
size	サイズ	KiCad EDA
slot	スロット	KiCad EDA
SMD	SMD	KiCad EDA
SMD pads	SMDパッド	KiCad EDA
solder	ハンダ	KiCad EDA
solder mask	ハンダマスク	KiCad EDA
Solid	実線	KiCad EDA
Spoke	スポーク	KiCad EDA
support	サポート	KiCad EDA
text	テキスト	KiCad EDA
Thermal relief	サーマルリリーフ	KiCad EDA
Thermal reliefs	サーマルリリーフ	KiCad EDA
Through-hole	スルーホール	KiCad EDA
Tolerance	誤差	KiCad EDA
Top	上	KiCad EDA
Total	合計	KiCad EDA
Track	配線	KiCad EDA
Track	配線	KiCad EDA
track	配線	KiCad EDA
Tracks	配線	KiCad EDA
type	タイプ	KiCad EDA
Type	タイプ	KiCad EDA
Value	値	KiCad EDA
Version	バージョン	KiCad EDA
version	バージョン	KiCad EDA
Via	ビア	KiCad EDA
Via Hole	ビア穴	KiCad EDA
vias	ビア	KiCad EDA
Vias	ビア	KiCad EDA
Warning	警告	KiCad EDA
Width	幅	KiCad EDA
Wildcards	ワイルドカード	KiCad EDA
zero	ゼロ	KiCad EDA
zone	ゾーン	KiCad EDA
zones	ゾーン	KiCad EDA

String information

Source string location

pcbnew/dialogs/panel_setup_rules_help_md.h:2

String age

3 months ago

Last updated

3 weeks ago

Source string age

3 months ago

Translation file

translation/pofiles/ja.po, string 7031